1. Field of the Invention
The invention relates to a memory system for non-volatile data storage and, more particularly, to a memory system that provides reading and programming with high density.
2. Description of the Related Art
Memory cards are commonly used to store digital data for use with various products (e.g., electronic products). Typically, these memory cards are non-volatile memories which are very popular and useful because they retain data even after being powered-off. Examples of memory cards are flash cards that use Flash type or EEPROM type memory cells to store the data. Flash cards have a relatively small form factor and have been used to store digital data for products such as cameras, hand-held computers, set-top boxes, hand-held or other small audio players/recorders (e.g., MP3 devices), and medical monitors. A major supplier of flash cards is SanDisk Corporation of Sunnyvale, Calif.
These memory cards are increasingly called on to store greater and greater amounts of data. Consequently, individual storage elements within these memory cards have been developed to support multiple levels so as to effectively store multiple bits of data. Traditional storage elements store only two states, while multiple level or high density storage elements store more than two states (e.g., four states).
Besides increasing storage capacities of memory cards, there is also a continuing need to provide higher and higher performance operation. Namely, there is a need to improve the speed by which data can be read from or written to a memory card. Since the reading or programming of memory cells within memory is able to be performed with some degree of parallelism, the improved performance can come through increased parallelism. However, increased parallelism is not merely a matter of increasing hardware components, instead precise cells control and management of inter bit line interference must be considered. However, to obtain increased parallelism requires consideration of many complex characteristics of the memory cards, such as precise cell control and inter bit line interference.
Thus, there is a need for improved approaches to reading or writing data to a memory array with a greater degree of parallelism.
The invention relates to a memory system (e.g., memory card) in which density for reading and programming (writing) of dual cell memory elements is enhanced. According to one aspect of the invention, all bit lines for the memory system can be productively used during reading or programming so as to achieve improved (e.g., maximum) parallelism of read and/or program operations. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.
The invention can be implemented in numerous ways. For example, the invention can be implemented as a system, device or method. Several embodiments of the invention are discussed below.
As a non-volatile semiconductor memory device, one embodiment of the invention includes at least: a plurality of bit lines; a plurality of word lines; and a plurality of dual cell storage elements. Each of the dual cell storage elements includes at least a source device, a drain device and a select device. Advantageously, two out of a total of six of the source devices and the drain devices in three adjacent dual cell memory units along a particular one of the word lines are able to be programmed or read simultaneously.
As a portable memory card, one embodiment of the invention includes at least a data storage array and a controller. The data storage array includes at least a plurality of bit lines, a plurality of word lines, and a plurality of dual cell storage elements. Each of the dual cell storage elements includes at least a source device, a drain device and a select device. The controller operates to control reading and writing to the data storage array. Two of the source devices and the drain devices in three adjacent dual cell storage elements along a particular one of the word lines are able to be programmed or read simultaneously.
As a method for reading data from a non-volatile memory, one embodiment of the invention includes at least: identifying three adjacent memory elements along a particular word line, each of the three adjacent memory elements being coupled between an adjacent pair of bit lines, each of the three adjacent memory elements including at least a pair of memory cells; coupling one of the bit lines in each of the adjacent pairs of the bit lines surrounding each of two of the three adjacent memory elements having a memory cell to be read to a low potential; coupling a read voltage to the memory cell to be read in each of two of the three adjacent memory elements having a memory cell to be read; coupling an overdrive voltage to the other memory cells in the three adjacent memory cells; and thereafter simultaneously reading data from one of the two memory cells in the two of the three adjacent memory elements having a memory cell to be read via another of the bit lines in each of the adjacent pairs of the bit lines surrounding each of two of the three adjacent memory elements having a memory cell to be read.
As another method for reading data from a non-volatile memory, one embodiment of the invention includes at least: providing a non-volatile memory having an array of memory elements, a plurality of bit lines, a plurality of word lines, and a plurality of gate control signals; identifying first, second and third memory elements that are adjacent one another along a particular word line, each of the first, second and third memory elements including at least a pair of memory cells and a select gate; identifying first, second, third and fourth bit lines that are adjacent one another along the particular word line, the first memory element being interposed between the first bit line and the second bit line, the second memory element being interposed between the second bit line and the third bit line, and the third memory element being interposed between the third bit line and the fourth bit line; identifying a first memory cell in the first memory element and a second memory element in the third memory element to be read; coupling the first bit line and the fourth bit line to a low potential; coupling the other memory cells in the first, second and third memory elements other than the first and second memory cells to a high potential; coupling the particular word line to the select gates for the each of the first, second and third memory elements; coupling a read voltage to the first and second memory cells to be read; and thereafter simultaneously reading data from one of the first and second memory cells via the second and third bit lines.
As a method for programming data to a non-volatile memory, one embodiment of the invention includes at least: identifying three adjacent memory elements along a particular word line, each of the three adjacent memory elements being coupled between an adjacent pair of bit lines, each of the three adjacent memory elements including at least a pair of memory cells; coupling one of the bit lines in each of the adjacent pairs of the bit lines surrounding each of two of the three adjacent memory elements having a memory cell to be programmed to a program level potential; coupling the other of the bit lines in each of the adjacent pairs of the bit lines surrounding each of two of the three adjacent memory elements having a memory cell to be programmed to a low potential; coupling a program gate voltage to the memory cell to be programmed in each of two of the three adjacent memory elements having a memory cell to be read; coupling an overdrive voltage to the other memory cells in the three adjacent memory cells; and thereafter simultaneously programming data to one of the two memory cells in the two of the three adjacent memory elements having a memory cell to be programmed.
As another method for programming data to a non-volatile memory, one embodiment of the invention includes at least: providing a non-volatile memory having an array of memory elements, a plurality of bit lines, a plurality of word lines, and a plurality of gate control signals; identifying first, second and third memory elements that are adjacent one another along a particular word line, each of the first, second and third memory elements including at least a pair of memory cells and a select gate; identifying first, second, third and fourth bit lines that are adjacent one another along the particular word line, the first memory element being interposed between the first bit line and the second bit line, the second memory element being interposed between the second bit line and the third bit line, and the third memory element being interposed between the third bit line and the fourth bit line; identifying a first memory cell in the first memory element and a second memory element in the third memory element to be programmed; coupling the first bit line and the fourth bit line to a program level potential; coupling the other memory cells in the first, second and third memory elements other than the first and second memory cells to a high potential; coupling the particular word line to the select gates for the each of the first, second and third memory elements; coupling a program voltage to the first and second memory cells to be programmed; and thereafter simultaneously programming data to the first and second memory cells.
Other aspects and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the invention.